We implement a premilinary design in UMC 28nm process.
The simulation result shows a 316mVpk (Poout = 0dBm) swing can be achieved at ANT load
The next question is how to implement the design with only digital std-cell. We first try to tackle this problem for the 60GHz frequency generator:
As the FO4 delay of UMC28 is in order of 10 ps, it is clearly impractical to employ digital logic implementation since the RC delay will corrupt any digital transition at 60GHz. Hence, we need to stick with the initial current mode generator scheme. In order to implement the half NMOS NAND circuit, we can use the std-cell NAND gate with VDD tied to OUTPUT node to deactivate PMOS part:
Only drawback of this is the extra loading of PMOS parasitic cap at the low impedance 60GHz output node. This will reduce the output swing.The final swing at ANT output with this implemenation is 220mV ~ -3dBm.
ANT output waveform:
Next task will be the implementation of diff-pair preamplifier stage using all std-cell implementation.
Another aspect is the power consumption and effiency of the 60GHz TX. A summary of current consumption break-down from each block is as followed:
Since current consumption is pretty high and efficiency is poor, we need to further study to optimize the power consumption...