Richard Lin (Ducky)
Postdoc
Email: richardlin [at] g [dot] ucla [dot] edu
Website: https://ducky64.github.io
Research
I'm interested in improving device design (primarily at the circuit board level) by integrating ideas from software engineering. The current project is a hardware description language for boards that automates the low-level details of design and provides meaningful design re-use, supported by graphical tooling in an integrated development environment (IDE) that bridges familiar schematic-like views.
My work takes an interdisciplinary approach, blending techniques from human-computer interaction (HCI), programming languages (PL) and electrical engineering (EE).
Education
B.S. Electrical Engineering and Computer Science, UC Berkeley, 2013
Ph.D. Computer Science, UC Berkeley, 2021
Blog posts
- 11/02/2023 : Advanced PCBs and IoT ... soldering iron?
- 05/11/2023 : Circuit Board HDL - Open Hardware Summit talk and packaging release
- 11/12/2022 : UIST, SCF, and Demo Engineering
- 10/14/2022 : Updated board HDL tutorial
- 09/30/2022 : Something completely different: programming languages... for nametag and labels?!
- 09/02/2022 : Infinity Refactoring: revenge of the connect algorithm
- 08/12/2022 : Board Design Language Infrastructure Week
- 07/29/2022 : Using computationally designed boards - in the field!
- 06/14/2022 : The LED matrix works!
- 06/08/2022 : Bringing up the BLE multimeter board, revision 2
- 06/01/2022 : Optimizing board designs with multipack devices
- 05/24/2022 : More Boards! Charlieplexed LED Matrix
- 05/09/2022 : The refactoring never ends: updating the IDE
- 04/25/2022 : Putting together the last 3 months of work: the BLE voltmeter example board
- 04/19/2022 : Limitations of mypy for statically checking array-valued types
- 04/12/2022 : Array-to-array connections
- 04/02/2022 : End-to-end port arrays with new microcontroller definition!
- 03/26/2022 : Weekly WIP: Concept to green tests: port arrays across levels of hierarchy
- 03/19/2022 : Weekly WIP: Port arrays across levels of hierarchy
- 03/11/2022 : Weekly WIP: Plumbing Through Block-side Port Arrays
- 03/04/2022 : Weekly WIP: Towards Block-side Port Arrays
- 02/19/2022 : Simplifying generator semantics for the board design HDL
- 02/11/2022 : Firmware Friday: Engineering the SMU and Multimeter Examples
- 02/04/2022 : Simplifying the electronics design data model
- 01/28/2022 : Board Design Tools for the 21st Century and Introductions
